The present invention relates to a semiconductor integrated circuit device incorporating a multiplicity of logic gates. More particularly, the present invention pertains to a semiconductor integrated circuit device which is suitable for achieving a large-scale integration, a low power consumption and a high-speed operation.
As a semiconductor integrated circuit device for realizing a logic consisting of a multiplicity of logic gates, a gate array is widely known. A general arrangement of the gate array is shown in FIG. 2. Rows 202 of basic cells are arrayed on an LSI chip. A region 203 for interconnection, which is known as an interconnection channel region, is provided between each pair of adjacent rows 202 of basic cells. A region for input and output circuits and bonding pads is prepared around the cell array. Logic gates which are prepared in advance are connected in accordance with a logic which is desired to be realized. Logic gates on a logic diagram representing a logic which is desired to be realized are related to basic cells on the gate array and the related basic cells are interconnected according to CAD (Computer Aided Design) in general. The gate array has the advantage that the time required for designing and production thereof can be reduced since the interconnection step alone needs to be customized.
Examples of circuits for basic cells include TTL, ECL, CMOS and Bi-CMOS gate arrays. TTL, ECL and CMOS gate arrays are described in Saburo Muroga "VLSI System Design", Wiley Japan, 1984. An example of the arrangement of a two-input NAND gate in a CMOS gate array is shown in FIG. 3. In this figure, the reference numerals 301, 302 denote PMOS transistors, and 303, 304 denote NMOS transistors. A basic gate in the Bi-CMOS gate array is described in the specification of European Patent Laid-Open No. 0099100 1/1984. An example of the arrangement of a two-input NAND gate in a Bi-CMOS is shown in FIG. 4.
All the TTL, ECL and Bi-CMOS gate arrays described in the above-described literatures are constituted by basic gates and basic cells which are arranged in accordance with one kind of circuit format, and there has heretofore been no gate array in which a plurality of kinds of circuit are mixed together in accordance with a particular purpose.
In FIG. 4, the reference numerals 401, 402 denote PMOS transistors, while 403, 404 denote NMOS transistors, and 405, 406 denote NPN transistors.
There are three important indexes of performance of integrated circuit devices of the types described above, that is, delay time, power consumption and chip size. The characteristics in regard to delay time and power consumption of ECL, CMOS and Bi-CMOS gates are summarized in FIG. 9. The ECL gate shows the highest speed but has a relatively large power consumption. On the other hand, the CMOS gate has a relatively large delay time but has a power consumption which is about two orders smaller than that of the ECL gate. The Bi-CMOS gate has substantially the same power consumption as that of the CMOS gate but is smaller in delay time than the latter.
FIG. 5 shows the characteristics in regard to delay time of the Bi-CMOS and CMOS gates. Within a region of relatively low capacitance, the CMOS gate is higher in speed than the Bi-CMOS gate, but in a region of relatively high capacitance the latter is higher in speed than the former. This is because the parasitic capacitance, such as the collector capacitance, of bipolar transistors is larger than that of CMOS transistors although the load driving capacity of the former exceeds that of the latter.
As to the basic cell area, the CMOS gate has the smallest size, and the size of the Bi-CMOS gate is about double that of the CMOS gate, while the size of the ECL gate is several times as large as that of the CMOS gate. In other words, the scale of integration becomes smaller in the order, the CMOS, Bi-MOS and ECL gates.
More specifically, the CMOS basic gate has the largest scale of integration but involves the problem that the operation speed is relatively low when the capacitive load (hereinafter referred to simply as "load") is relatively heavy. The Bi-CMOS basic gate is relatively high in speed when the load is relatively heavy, but the operation speed thereof is lower than that of the CMOS basic gate in a region of relatively light load. In addition, the Bi-CMOS basic gate has the disadvantage that the basic cell area is relatively large and the scale of integration thereof is smaller than that of the CMOS basic gate.